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Home Capability Rigid PCBs (RoHS and Non-RoHS) - Medium Volume

Capability

QualiEco Circuits specialises in smart yet simple PCB solutions – we're always one step ahead in technology and innovation. Rigid PCBs Medium Volume – In detail

Prototype PCBsStandard PCBsDescription

TOPPCB Details
  • Max. no. of layers1 to 12 LayersUp to 30 Layers
  • Max. board size (L x W) in mm600mm x 500mm600mm x 1100mm
  • Max. board thickness (in mm.)6mm6mm
  • Min. finished board thickness (in mm.)0.4mm0.3mm
  • Min. Core Thickness0.2mm0.1mm
  • Min. Dielectric0.05mm0.05mm
TOPBase Material
  • (A) Base MaterialFR4 (Std, High Tg & HF)FR4 (Std, High Tg & HF)
  • (B) Inner layer Copper cladding  
  • * Max. Cu Wt. For Planes (Oz.)70µm (2oz)70µm (2oz)
  • * Max. Cu Wt. For Signals (Oz.)70µm (2oz)70µm (2oz)
  • * Min. Cu Wt. (Oz.)18µm18µm
  • (C) Outer layer Copper cladding  
  • *Max Cu Wt. (Oz.)210µm (6oz)210µm (6oz)
  • *Min Cu Wt. (Oz.)18µm18µm
TOPEtching
  • Minimum (in mils)Trace WidthSpacingTrace WidthSpacing
  • For copper thickness of 0.5 Oz5mil5mil4mil4mil
  • For copper thickness of 1.0 Oz6mil6mil5mil5mil
  • For copper thickness of 2.0 Oz7mil7mil6mil6mil
  • For copper thickness of 3.0 Oz9mil9mil8mil8mil
TOPDrilling
  • Min. finished via hole size    
  • Mechanical Drilling0.2mm0.2mm
  • Laser Drilling- N/A -- N/A -
  • Min. finished via pad size0.5mm0.5mm
  • Min. annular ring (via holes)5 mils5 mils
  • Min. annular ring (Component holes)8mil8 mils
  • Min. hole size tolerance (in mils)PTHNPTHPTHNPTH
  • Hole size < 0.024"+/-0.076mm+/-0.05mm+/-0.076mm+/-0.05mm
  • Hole size > 0.024" < 0.138"+/-0.076mm+/-0.05mm+/-0.076mm+/-0.05mm
  • Hole size > 0.138"+/-0.076mm+/-0.05mm+/-0.076mm+/-0.05mm
  • Blind & Buried vias manufacturableYESYES
  • Drill to track clearance for inner layers0.25mm (4L)
    0.30mm (6L)
    0.40mm (8L)
    0.50mm (10L)
    0.25mm (4L)
    0.30mm (6L)
    0.40mm (8L)
    0.50mm (10L)
  • Min. annular ring (Component holes)0.2mm to 0.4mm0.2mm to 0.4mm
TOPPlating / Surface Treatment
  • HASLYESYES
  • Electrolytic GoldYESYES
  • Electroless Nickel / GoldYESYES
  • SMOBC with OSP (Entek Coating)YESYES
  • Immersion SilverYESYES
  • Immersion TinYESYES
TOPLayer construction & Impedance Design
  • Min. core thickness0.1mm (H/H oz)0.1mm (H/H oz)
  • Preferred varieties of Thin core laminates generally stocked (in mils)0.1/ 0.13/ 0.15/ 0.2/ 0.27/ 0.3/ 0.35/ 0.4/ 0.5/ 0.6/ 0.8/ 1.0/ 1.2mm

    4, 20, 24, 28, 47.24 & 59mil
    0.1/ 0.13/ 0.15/ 0.2/ 0.27/ 0.3/ 0.35/ 0.4/ 0.5/ 0.6/ 0.8/ 1.0/ 1.2mm

    4, 20, 24, 28, 47.24 & 59mil
  • Prepregs generally stocked (in mils)3, 5 & 7mil3, 5 & 7mil
TOPMaximum Fabrication Tolerance
  • Maximum Fabrication Tolerance+/-10% of finished board thickness+/-10% of finished board thickness
TOPSolder mask
  • Mask opening (pad + XXX)3mil3mil
  • Min. solder mask web width between pads6mil4mil
  • PAD to PAD min. space if web required3mil3mil
  • SM clearance to PAD4mil4mil
  • Min. SM thickness8µm8µm
TOPComponent Reference (Silk Screen)
  • Legend (Silk Screen) line width≥6mil4mil
  • Min. character height≥0.8mm≥0.8mm
  • Min. character spacing≥6mil≥5mil
TOPElectrical Test
  • CAD net list testing (IPC356D)PossiblePossible
  • Min. SMD pitch testable0.4mm0.4mm
  • Min SMD pad width testable0.2mm0.1mm
  • Max testing area (mm x mm)600mm x 600mm600mm x 600mm
  • Testing voltage250V DC250V DC
  • Open resistance20MΩ20MΩ
  • Short resistance50MΩ50MΩ
  • Top and Bottom Test simultaneouslyYESYES
TOPControlled Impedance measurement
  • Controlled Impedance measurementYESYES
TOPInner Layers (VCC and GND Layers)
  • Minimum Isolation from finished Drill0.25mm (4L)
    0.30mm (6L)
    0.40mm (8L)
    0.50mm (10L)
    0.25mm (4L)
    0.30mm (6L)
    0.40mm (8L)
    0.50mm (10L)
  • Up to 8 Layers (Single Stage bonding)0.26mm0.21mm
  • Up to 8 Layers (Two times bonding)0.26mm0.23mm
  • Up to 8 layers (more than two times)0.26mm0.23mm
  • Above 8 layers(Single Stage bonding)0.26mm0.26mm
  • Min. Annular ring for thermal pads0.31mm0.26mm
  • Min. Thermal Air Gap0.3mm0.25mm
  • Cu area to PCB edge clearance0.4mm0.25mm
TOPInner Layers (Signal Layers)
  • Minimum Annular Ring0.15mm0.13mm
  • Finished Drill to Track clearance  
  • Up to 8 Layers (Single Stage bonding)0.25mm0.21mm
  • Up to 8 Layers (Two times bonding)0.31mm0.26mm
  • Up to 8 layers (more than two times)0.36mm0.31mm
  • Above 8 layers(Single Stage bonding)0.26mm0.31mm
  • Cu area to PCB edge clearance0.4mm0.25mm
TOPScoring (V-cut)
  • Score line to Cu area clearance0.3mm0.25mm
TOPRouting
  • Minimum router diameter0.8mm0.8mm
  • Cu area to PCB edge clearance (Outer Layer)0.25mm0.15mm
  • Cu area to PCB edge clearance (Inner Layer)0.25mm0.25mm
TOPSlot
  • Minimum slot size0.8mm0.8mm

 

1. We prefer min. pad size >= hole size + 0.50 mm for any PTH hole.
2. NPTH holes should preferably not have any pad around them.
3. Jump scoring and depth routing possible – conditions apply

PCB Design Tips

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We have capability to manufacture Single Sided/Layer (SS), Double Sided/Layer (DS-NPTH & DS-PTH) and MultiLayer (up to 24 layers) PCBs with RoHS as an option.

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PCB Design Tips

PCB Design Tips

When designing a PCB, try to limit the amount of draws you use. Draws use a lot of memory and slow the programming time. Use a flash for pads instead.

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